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E2F0023-18-Z1
Semiconductor MSM7654
Semiconductor NTSC/PAL Digital Video Encoder
This version: Dec. 1998 MSM7654
Pr el im in ar y
GENERAL DESCRIPTION
The MSM7654, which is a digital video encoder supporting NTSC/PAL formats, converts digital image data to an analog video signal. The encoder can receive the digital image or RGB digital image signals conforming to ITU-R BT601 as an input signal. The encoder can output simultaneously the composite video and S-video signals, and it can also output the RGB analog signal by switching. The encoder can control luminance (Y) signal output levels of the composite video and S-video signals.
FEATURES
* Video signal system: NTSC/PAL * Scanning system: interlaced/noninterlaced (NTSC : 262 lines/PAL : 312 lines) * Input digital level: conforms to ITU-R601 (CCIR601) * Input-output timing: conforms to ITU Rec. 656 or ITU-R BT624-4 * Input signal sampling ratio : Y:Cb:Cr = 4:2:2 or 4:1:1/R:G:B = 8:8:8 * Supported input interface * ITU Rec. 656 * YCbCr format (8-bit input) * ITU-R601 (8-bit (Y) + 8-bit (CbCr) input) * RGB (24-bit input) * Pixel frequency (Sampling frequency) : * 12.272727 MHz (24.54545 MHz) : NTSC Square Pixel * 13.5 MHz (27 MHz) : NTSC/PAL ITU-R BT601 * 14.31818 MHz (28.63636 MHz) : NTSC 4Fsc * 14.75 MHz (29.5 MHz) : PAL Square Pixel * Output format * Selectable composite & S-video or RGB * 37.5 W driving capability * Master or slave operation (slave operation only in ITU Rec.656 mode) * Internal 3ch 10-bit DAC * 3-bit title graphics can be displayed (only for composite and S-video signals) * Color bar function * I2C-bus host interface function * Brightness level adjust of 100% to 68.75% (only for composite and S-video signals) * CENLOCK control * 3.3 V single power supply (each I/O pin is 5 V tolerable) * Package 64-pin plastic QFP (QFP64-P-1414-0.80-2K) (Product name: MSM7654GA)
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MSM7654
APPLICATIONS
* Video CD * Video game equipment * Electronic still cameras * Video filing systems * Video cameras * Videophones * Multimedia equipment * Video printers * Videoconferencing systems * Scanners * Video graphics boards * Monitoring systems
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RESET_L
BLOCK DIAGRAM
Semiconductor
OLC Black & Blank Pedestal DAC Interpolator + LPF Interpolator + LPF LPF Color Burst Generator Subcarrier Generator
OLR OLG OLB
YUV Color Generator
YA (R)
YD[7:0] Overlay Control
Y Level Converter
U Level Converter
CD[7:0] YUV to RGB Converter
Prologue Block
DAC
OVBSO (G)
V Level Converter
BD[7:0] DAC CA (B) XVREF I2C Control Logic Test Control Logic FS COMP
RGB Level Converter
VSYNC_L HSYNC_L CSYNC_L BLANK_L CLKX2
Sync Generator & Timing Controller
MS SCL
GENLOCK RGBMODE MODE[3:0]
SDA
TENB
OUTSEL
MSM7654
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MSM7654
PIN CONFIGURATION (TOP VIEW)

64 DGND 63 AVDD DVDD SDA SCL 1 2 3 4 RGBMODE MODE3 MODE2 MODE1 MODE0 MS 5 6 7 8 9 GENLOCK CSYNC_L 10 11 VSYNC_L 12 HSYNC_L BLANK_L DVDD 13 14 15 DGND 16 17 CD0(R0) 18 CD1(R1)
60 CVBSO
54 XVREF
56 COMP
49 DGND 48 DVDD 47 OUTSEL 46 CLKX2 45 TENB 44 RESET_L 43 FOUT 42 BD7(B7) 41 BD6(B6) 40 BD5(B5) 39 BD4(B4) 38 BD3(B3) 37 BD2(B2) 36 BD1(B1) 35 BD0(B0) 34 DVDD 33 DGND YD7(G7) 32
61 AGND
57 AGND
59 AVDD
51 OLG 30 YD5(G5)
19
20
21
22
23
24
25
26
27
28
29
CD2(R2)
CD3(R3)
CD4(R4)
CD5(R5)
CD6(R6)
CD7(R7)
YD0(G0)
YD1(G1)
YD2(G2)
YD3(G3)
YD4(G4)
64-Pin Plastic QFP
YD6(G6)
31
50 OLR
53 OLC
52 OLB
62 YA
58 CA
55 FS
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MSM7654
PIN DESCRIPTIONS
Pin 1 2 3 4 5 to 8 I/O I I I I/O Symbol DVDD SDA SCL RGBMODE MODE[3:0] 3.3 V digital power supply. I2C interface data bus. I2C interface clock bus. Input signal select pin. "0" : YCbCr / "1" : RGB, Internal pull-down. Operation mode select pin. However, sleepmode is valid while RGBMODE is "0". 0000 : NTSC ITU-R656 0010 : NTSC 24.52 MHz Square Pixel 0101 : NTSC 13.5 MHz YCbCr 0111 : NTSC 14.32 MHz 1000 : PAL ITU-R656 1010 : PAL 29.5 MHz Square Pixel 1110 : PAL 14.75 MHz 9 10 11 12 13 14 15 16 17 to 24 I I I I/O O I/O I/O I MS GENLOCK CSYNC_L VSYNC_L HSYNC_L BLANK_L DVDD DGND CD0 to CD7 pull-down. "1" : Master / "0" : Slave GENLOCK signal I/O pin. Composite sync output pin. Vertical sync input/output pin (ITU656: 0, others: I/O) Horizontal signal input/output pin (ITU656: 0, others : I/O) Composite blank signal input pin. 3.3 V digital power supply. Digital GND. 8-bit digital image chrominance signal data input pins at pixel rate operation. Level conforms to ITU-601. R signal input pins in RGB input mode. CD7 is MSB. Fixed to "0" when not used. 25 to 32 I YD0 to YD7 8-bit digital image data input pins at double pixel rate operation. 8-bit digital luminance signal data input pinsat pixel rate operation. Level conforms to ITU-601. G signal input pins in RGB input mode. YD7 is MSB. 33 34 35 to 42 43 44 45 46 47 48 49 50 I I I O I I I I DGND DVDD BD0 to BD7 FOUT RESET_L TENB CLKX2 OUTSEL DVDD DGND OLR Digital GND 3.3 V digital power supply B signal input pins in RGB input mode. Fixed to "0" when not used. Field information output pin (Odd Field : "1", Even Field : "0") (Polarity can be changed by the internal register.) System reset pin. Input pin for testing. Normally fixed to "0". Internal pull-down. Clock input pin. Video output format select pin. "0" : S-Video & Composite / "1" RGB. Internal pull-down. 3.3 V digital power supply Digital GND Overlay text color (Red component). 1001 : PAL 27 MHz YcbCr 1101 : PAL 13.5 MHz 1111 : Sleep Mode 0001 : NTSC 27 MHz YCbCr 0011 : NTSC 28.64 MHz 4Fsc 0110 : NTSC 12.27 MHz Description
Master/slave operation selection in other modes than CCIR656. Internal
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MSM7654
PIN DESCRIPTIONS (continued)
Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 O O O I/O I I I I/O I I Symbol OLG OLB OLC XVREF FS COMP AGND CA AVDD CVBSO AGND YA AVDD DGND Description Overlay text color (Green component). Overlay text color (Blue component). Transparent control signal. "1" indicates overlay signal. Reference voltage input pin for external DAC or internal reference voltage output pin. (Reference voltage for DAC) DAC full scale adjustment pin. DAC phase correction pin. Analog GND. Analog color chrominance signal output pin or B (Blue) signal output pin. 3.3 V analog power supply. Analog composite signal output pin or G (Green) signal output pin. Analog GND. Analog luminance signal output pin or R (Red) signal output pin. 3.3 V analog power supply. Digital GND.
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ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Digital Input Voltage Analog Output Current Power Consumption Storage Temperature Symbol DVDD AVDD VI IO PW TSTG Condition -- -- DVDD = 3.3 V -- -- -- Rating -0.3 to +4.5 -0.3 to +4.5 -0.3 to +5.5 50 700 -55 to +150 Unit V V mA mW C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage (*1) "H" Level Input Voltage "L" Level Input Voltage Operating Temperature 1 External Reference Voltage DA Current Setting Resistance DA Output Load Resistance Symbol DVDD AVDD VIH VIL Ta1 Vrefex Riadj RL Condition -- -- -- -- DVDD = AVDD = 3.3 V DVDD = AVDD = 3.3 V, Ta = 25C (*2) (*3) Min. 3.0 3.0 2.2 -- 0 -- -- -- Typ. 3.3 3.3 -- -- 25 1.25 197.5 (75//75) Max. 3.6 3.6 -- 0.8 70 -- -- -- Unit V V V C V W W
(*1) (*2) (*3)
Supply an equal voltage to both DVDD and AVDD. A volume control resistor of approx. 500 W is recommendable for adjusting the output current. Indicates the value when Riadj = 197.5 W (typical value).
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ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta = 0 to 70C, DVDD = 3.3 V 0.3 V, AVDD = 3.3 V 0.3 V) Parameter "H" Level Output Voltage "L" Level Output Voltage Input Leak Current Output Leak Current Power Supply Current (operating) Power Supply Current (standby) Power Supply Current (Sleep mode) I2 C-bus SDA Output Voltage I2C-bus SDA Output Current Internal Reference Voltage DA Output Load Resistance Integral Linearity Differential Linearity Symbol VOH VOL II IO IDDO IDDS IDDSM SDAVL SDAIO Vrefin RL SINL SDNL Condition IOH = -4 mA (*1) IOL = 4 mA (*1) VI = GND to DVDD VI = GND to DVDD (*2) -- RESET_L = "L" CLKX2 = 0 MHz MODE [3:0] = 0000 Low level, IOL = 3 mA During Acknowledge -- 75 W//75 W -- -- 0 3 -- Min. 0.7VDD -- -10 -10 -- -- Typ. -- -- -- -- 140 60 0.5 -- -- 1.25 37.5 2 1 Max. -- 0.4 +10 +10 160 65 5 0.4 -- -- Unit V V mA mA mA mA mA V mA V W LSB LSB
(*1) (*2)
VSYNC_L, HSYNC_L, GENLOCK, CSYNC.L, FOUT SDA
AC Characteristics
(Ta = 0 to 70C, DVDD = 3.3 V 0.3 V, AVDD = 3.3 V 0.3 V) Parameter Symbol Condition PAL Square Pixel CLKX2 Frequency (*1) Fclk NTSC 4Fsc NTSC Square Pixel ITU-R601/656 Input Data Setup Time Input Data Setup Time Input Data Hold Time Input Data Hold Time Pulse Width Output Delay Time Output Delay Time2 I2C-bus Clock Cycle Time I C-bus High Level Cycle I2C-bus Low Level Cycle
2
Min. -- -- -- -- 7.0 0.0 5.0 11.08 93.0 5.0 6.0 200 100 100
Typ. Max. 29.5
28.63636 24.54545
Unit MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns
-- -- -- -- -- -- -- -- -- 15.0 20.0 -- -- --
27.0 -- -- -- -- -- -- -- -- -- --
ts1 ts2 th1 th2 tw td1 td2 tC_SCL tH_SCL tL_SCL
-- -- -- -- -- -- -- Rpull_up = 4.7 kW Rpull_up = 4.7 kW Rpull_up = 4.7 kW
(*1)
If high precision is needed for sub-carrier/synchronization signals, clocks within 100 ppm(typ.) should be provided.
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Semiconductor
INPUT/OUTPUT TIMING
Input timing
CLKX2
HSYNC_L, VSYNC_L, BLANK_L, YD, CD, BD, MS, RGBMODE, MODE, OLR, OLG, OLB, OLC, TENB, OUTSEL GENLOCK
Output timing (1) HSYNC_L, VSYNC_L CSYNC_L, GENLOCK
,
TS = 1/Fclk ts1 Invalid data th1 ts2 tw th2 td1 td2 valid data
8 9 ACK tC_SCL 1 tL_SCL 2 3-8 tH_SCL 9 ACK
MSM7654
FOUT
I2C-bus Interface Input/Output Timing The following figure shows I2C-bus basic input/output timing.
SDA SCL
MSB
S Start Condition
1
2
7
P Stop Condition
Data Line Stable: Data Valid Change of Data Allowed
I2C-bus Basic Input/Output Timing
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Semiconductor FOUT output timing (1) In master mode
CLKX2 1CLKX2 HSYNC_L VSYNC_L FOUT CLKX2 1CLKX2 HSYNC_L 1/2H VSYNC_L FOUT
MSM7654
(2) In slave mode
CLKX2 Tfout HSYNC_L VSYNC_L FOUT CLKX2 Tfout HSYNC_L 1/2H VSYNC_L FOUT
Tfout values in slave mode depend on pixel rates. The following table lists the Tfout value to each pixel rate.
Input interface CCIR Rec.656 YCbCr (8bit) YCbCr (16bit) RGB 5 clkx2 9 clkx2 9 clkx2 or 10 clkx2 9 clkx2 or 10 clkx2 Tfout
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Semiconductor GENLOCK I/O timing (1) Input timing
CLKX2 Tgen GENLOCK Internal CLKX1 Genlock flag HSYNC_L (Input) VSYNC_L (Input)
MSM7654
If the encoder is in the slave mode and the register MR1[0] is set to "0" (External pin Genlock control is valid), the subcarrier-phase reset signal can be input from the GENLOCK pin. If the GENLOCK pulse is input to the encoder in the NTSC mode, the subcarrier is reset when the fourth field is shifted into the first. And if the GENLOCK pulse is input to the encoder in the PAL mode, the subcarrier is reset when the eighth field is shifted into the first. The subcarrier-phase reset signal should be pulsed at the timing that meets the AC characteristics. 5 clkX2 pulses are required from the time the reset signal is input from the GENLOCK pin to when the internal GENLOCK flag is set. Thus, the subcarrier-phase will be reset if the GENLOCK pulse is input 5 clkx2 pulses before HSYNC_L and VSYNC_L fall when the internal state of the encoder is the fourth field. The subcarrier-phase, however, cannot be reset if the GENLOCK pin is fixed high. (2) Output timing (master mode)
CLKX2 4th or 8th field VSYNC_L (output) GENLCOK
If the encoder is in the master mode, the register MR1[0] is set to "1" (Internal register control is valid) and the register MR1[1] is set to "0" (Genlock on), the subcarrier-phase reset signal can be output from the GENLOCK pin. If the encoder is set to NTSC, the GENLOCK pulse will be output at the same timing as the HSYNC_L and VSYNC_L falling edges when the internal state of the encoder is the fourth field. And if the encoder is set to PAL, the GENLOCK pulse will be output at the same timing as the HSYNC_L and VSYNC_L falling edges when the internal state of the encoder is the eighth field.
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Semiconductor
MSM7654
BLOCK FUNCTIONAL DESCRIPTION
* Prologue Block This block separates input data at the ITU Rec.656 format into a luminance signal (Y) and a chrominance signal (Cb & Cr), and also generates information concerning sync signals HSYNC_L, VSYNC_L, and BLANK_L. This block separates input data at the 27 MHz YCbCr (8-bit input) format into a luminance signal (Y) and a chrominance signal (Cb & Cr). This block separates input data at the 13.5 MHz YCbCr (16-bit input) format into a chrominance signal Cb and a chrominance signal Cr. Of the processed input data, luminance and chrominance signals other than valid pixel data are replaced by 8'h10 and 8'h80 respectively. RGB signals are converted into luminance (Y) and chrominance (Cb & Cr) signals. * Y Limiter Block This block limits the luminance input signal by clipping the lower limit of an input signal outside the ITU601 Standard * Signals are limited to YD = 16 when YD < 16. * Signals are limited to YD = 254 when YD (input during a valid pixel period) = 255. In other cases, signals are fed as is to next processing. * C Limiter Block This block limits the chrominance signal by clipping the upper and lower limits of the input signal outside the ITU601 Standard. CD = 1 when CD = 0 is input during a valid pixel period. CD = 254 when CD = 255 is input during a valid pixel period. * Y Level Converter Converts ITU-601 standard luminance signal level to DAC digital input level. * U Level Converter Converts ITU-601 standard chrominance signal level to DAC digital input level. * V Level Converter Converts ITU-601 standard chrominance signal level to DAC digital input level. * RGB Level Converter Converts RGB signal level to DAC digital input level. * YUV Color Generator This block generates luminance and chrominance signals from overlay color signals OLR, OLG and OLB. Control signals (CR [2:0] ) control the output content (overlay or color bar) and output level (100%, 75%, 50%, 25%).
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Semiconductor
MSM7654
* Overlay Control This block selects input image data or YUV Color Generator output signals. It is determined by the level of the control signal (OLC, CR [2]), as shown below: (x : don't care) CR [2] = 1, OLC = x: Selects color bar signal (YUV Color Generator output signal). CR [2] = 0, OLC = 1: Selects overlay signal (YUV Color Generator output signal). CR [2] = 0, OLC = 0: Selects input image data. * YUV to RGB Converter This block converts YUV signals selected in the overlay control block into RGB signals. * Black & Blank Pedestal This block adds sync signals at the luminance side to luminance signals. * Interpolator + LPF This block executes data interpolation and the elimination of high frequency components by LPF for input chrominance signals. * I2C Control Logic This is the serial interface block based on I2C standard of Phillips Corporation. Internal registers MR and CR can be set from the master side. When writing to the internal registers other than MR [1] (black level control) and CR [1:0] (overlay level), written contents are immediately set to them. It is during the vertical blanking period that written contents are set to MR [1] and CR [1:0]. * Sync Generator & Timing Controller This block generates sync signals and control signals. This block operates in slave mode, which performs external synchronization, and in master mode, which internally generates sync signals. * Color Burst Generator Outputs U and V components of amplitude of burst signals. * Subcarrier Generator Executes color subcarrier generation. * Low Pass Filter (LPF) This block performs upsampling at CLKX2 for luminance signals and chrominance signals modulated with CLKX1 divided from CLKX2. Interpolation processing is executed in this process.
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INPUT DATA FORMAT
* Input Level 1 (Y CbCr format) The signal level specified by the ITU601 is input. When other signal levels than specified by the ITU601 are input, the luminance signal level is clipped to 16 to 254 and the chrominance signal level to 1 to 254. For chrominance signal input, the offset binary and 2's complement formats are available by setting of internal registers.
Digital Level 100% White level 235 240(112) Digital Level
128(0)
Black Level 16 Y data 16(-112) C data
Input luminance signal level
Input chrominance signal level
* Two Input Level 2 (RGB format) Two types of input level are available by setting of internal registers.
Digital Level Digital Level 100% White level 235 255
Black Level 16 Format 1 0 Format 2
Input RGB signal level 1
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Semiconductor
MSM7654
* Basic Pixel Sampling Ratio 4:2:2 or 4:1:1 is supported.
CLKX2 YD CD Y1 Cb1 Y2 Cr1 Y3 Cb3 Y4 Cr3 Y5 Cb5 Y6 Cr5
4:2:2 sampling at 8bit Y/8bit CbCr input
CLKX2 YD CD Y1 Cb1 Y2 Cr1 Y3 Y4 Y5 Cb5 Y6 Cr5
4:1:1 sampling at 8bit Y/8bit CbCr input
CLKX2 YD CD BD G1 R1 B1 G2 R2 B2 G3 R3 B3 G4 R4 B4 G5 R5 B5 G6 R6 B6
At RGB input
CLKX2 YD Cb1 Y1 Cr1 Y2 Cb3 Y3 Cr3 Y4 Cb5 Y5 Cr5 Y6
4:2:2 sampling at 8bit YCbCr input
CLKX2 YD Cb1 Y1 Cr1 Y2 Y3 Y4 Cb5 Y5 Cr5 Y6 Invalid data
4:1:1 sampling at 8bit YCbCr input 15/42
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MSM7654
INPUT TIMING 1 (ITUR656 input)
The input data is fetched in the encoder at the rising edge of a clock pulse.
CLKX2 DATA OLR, OLG, OLB, OLC
SAV(1st) SAV(2nd) SAV(3rd) SAV(4th) Cb0 Y00 Cr0 Y01 Cb1 Y10 Cr1 Y11 EAV(1st) EAV(2nd) EAV(3rd) EAV(4th)
don't care
VALID DATA
don't care
Input timing
RELATIONSHIP BETWEEN BLANK SIGNAL AND INPUT IMAGE DATA
The blank signal is generated by the ITU Rec.656 standard input data. The input image data is valid when the blank signal is "H".
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MSM7654
VALID DATA RANGE
According to the ITU Rec.656 standard, the pixel data immediately from SAV (4th word) to a fixed value before EVA is valid. The following figure shows the relationship between the input data at the CCIR Rec.656 format and the sync, luminance, chrominance signals which are processed inside the encoder.
Note) The values in parenthesis indicate values in PAL mode. 1716Tclkx2 (NTSC)/1728clkx2 (PAL) 1440T (NTSC/PAL)
SAV
EAV
ITU Rec.656 standard input data 4Tclkx2 Sync signal VSYNC_L (0H) generated by input signal Sync signal VSYNC_L (1/2H) generated by input signal Sync signal HSYNC_L generated by input data
Cb0, Y00, Cr0, Y01, Cb1, Y10, Cr1, Y11....
11Tclkx1 (4Tclkx1)
4Tclkx2
63Tclkx1 (63Tclkx1) 67Tclkx1 (67Tclkx1)
1/2H 4Tclkx1 (4Tclkx1)
9Tclkx1 (16Tclkx1) Sync signal BLANK_L generated by input data
127Tclkx1 (142Tclkx1) 136Tclkx1 (146Tclkx1)
711Tclkx1 (702Tclkx1)
EAV
20Tclkx1 (20Tclkx1) 20Tclkx1 (20Tclkx1)
127Tclkx1 (142Tclkx1) BLANK_L internally generated to assure the horizontal and vertical periods Luminance signal separated from input data Chrominance signal separated from input data 8'h10 8'h80
711Tclkx1 (702Tclkx1)
Y00 Y01 Y10 Y11 Cb0 Cr0 Cb1 Cr1 1H
8'h10 8'h80
Composite signal
Relationship between input data and sync signal, luminance signal, chrominance signals
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CLOCK TIMING2 (8bit Y/8bit CbCr input, 8bit YCbCr & RGB input)
Input Data Timing Input data and sync signals are fed into the encoder at the rising edge of CLKX2. Input data is handled as valid pixel data when tSTART passes after the falling edge of HSYNC_L. Chrominance signal of input data at this time is regarded as Cb.
ACTIVE VIDEO LINE tACT
tSTART CLKX2 HSYNC_L YD, CD, BD, OLR, OLB, OLG,OLC BLANK_L ts1 don't care
th1 don't care VALID DATA
Video data input timing Input data is recognized as valid pixel data when input signal BLANK_L is "H" in the tACT period. When BLANK_L is "H" during the blanking period, however, input data is not output as valid pixel data since processing to maintain blanking period is internally in-progress. The values of tSTART differ slightly between in master mode and in slave mode. The values of tSTART are as follows. In YCbCr format input mode, the values of tSTART are the same, in 8 bit (Y) + 8 bit (CbCr) mode or in 8 bit (YCbCr) mode.
In master mode Operation mode ITU 601 NTSC ITU 601 PAL 4 Fsc NTSC Square pixel NTSC Square pixel PAL tSTA - tS1 = tSTART tSTA(Ts) 250 280 266 228 306 In slave mode Operation mode ITU 601 NTSC ITU 601 PAL 4 Fsc NTSC Square pixel NTSC Square pixel PAL tSTA(Ts) 260 290 276 238 316
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Semiconductor Timing of Input Data to HSYNC_L
MSM7654
CLKX2 CLKX1O HSYNC_L OLR,OLG, OLB, OLC YD
Invalid Data Invalid Data tSTART Invalid Data Invalid Data Cb0 Y00 Cr0 tACT Y01 Valid Data Cb1 Y10
Input Timing when BLANK_L is Input
CLKX2 BLANK_L YD
Cb0 Y00 Cr0 Y01 Cb1
Input timing at double pixel rate YCbCr format Timing of Input Data to HSYNC_L
CLKX2 CLKX1O HSYNC_L OLR,OLG, OLB, OLC YD CD
Invalid Data Invalid Data Invalid Data tSTART Invalid Data Invalid Data Invalid Data Y0 Cb0 tACT Y1 Cr0 Valid Data Y2 Cb1
Input Timing when BLANK_L is Input
CLKX2 BLANK_L YD CD, BD
Y0 Cb0 Y1 Cr0 Y2 Cb1
Input timing at pixel rate and RGB YCbCr format 19/42
Semiconductor * VSYNC_L, HSYNC_L Input Timing Input timing of VSYNC_L and HSYNC_L in slave mode is as follows.
MSM7654
VSYNC_L
HSYNC_L -1/4H 0H 1/4H
(1) If the encoder detects the VSYNC_L falling edge between -1/4H and 0H (not including 0H), it judges information with HSYNC_L and VSYNC_L as an odd field and normally operates. (2) If the encoder detects the VSYNC_L falling edge between 0H and 1/4H (including 0H), it judges information with HSYNC_L and VSYNC_L as an odd field and mormally operates.
VSYNC_L
HSYNC_L -1/4H 0H 1/4H
(3) If the encoder detects the VSYNC_L falling edge between 1/4H and 1/2H (not including 1/ 2H), it judges information with HSYNC_L and VSYNC_L as an even field and normally operates. (4) If the encoder detects the VSYNC_L falling edge between 1/2H and 3/4H (including 1/2H), it judges information with HSYNC_L and VSYNC_L as an even field and normally operates. The normal vertical blanking periods cannot be obtained in the following cases: (1) The HSYNC_L period is longer than the specification (2) The HSYNC_L period is shorter than the specification (3) The VSYNC_L period is longer than the specification (4) The VSYNC_L period is shorter than the specification
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Semiconductor Internal Synchronization Output Timing Output timing of HSYNC_L and VSYNC_L in master mode is as follows.
MSM7654
CLKX2 td1 HSYNC_L VSYNC_L CSYNC_L td1
Output timing 1 of internal synchronization, HSYNC_L, VSYNC_L, and CSYNC_L
VSYNC_L
HSYNC_L
CSYNC_L
YA
523 524 525 1 2 3 4 5 6 7 17 18
G (with SYNC)
523 524 525 1 2 3 4 5 6 7 17 18
Output timing 2 of internal synchronization HSYNC_L, VSYNC_L, and CSYNC_L
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MSM7654
OUTPUT FORMAT
The timing conforms to the ITU624 standard. In the NTSC operation mode, the existence/non-existence of setup level is selected by setting of internal regsiters. Data level on the DAC input terminal: When the contents of 100% luminance order color bar are input into the encoder, the input level is as follows.
DAC data Lumi (IRE) 957 133
Composite Waveform (NTSC) Yellow White Cyan Green Magenta Red Blue Black
775 715 610 549 450 390 338 285 266 224 114 4
100 89 70 59 41 30 20 11 7.5 0 -20 -40
NTSC Composite Signal (Setup 7.5)
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Semiconductor
Y Waveform (NTSC) White 775 715 610 549 450 390 285 224 100 89 70 59 41 30 11 0 Yellow Cyan Green Magenta Red Blue
MSM7654
DAC data Lumi (IRE)
Black
4
-40
NTSC Y Signal Output (Setup 0)
DAC data Lumi (IRE) 858 836 754 622 512 402 270 188 166 63 59 44 20 0 -20 -44 -59 -63
C Waveform (NTSC) Yellow Cyan Green Magenta Red Blue
Color Burst
NTSC C Signal Output
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Semiconductor
Composite Waveform (PAL) Yellow White 973 133 Cyan Green Magenta Red Blue
MSM7654
DAC data Lumi (IRE)
Black
792 731 627 566 467 406 359 302 241 123 4
100 89 70 59 41 30 21.5 11 0 -21.5 -43
PAL Composite Signal
DAC data Lumi (IRE) 792 731 627 566 467 406 302 241 100 89 70 59 41 30 11 0
Y Waveform (PAL) White Yellow Cyan Green Magenta Red Blue Black
4
-43
PAL Y Signal Output
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MSM7654
DAC data Lumi (IRE) 858 836 754 630 512 394 270 188 166 63 59 44 21.5 0 -21.5 -44 -59 -63
C Waveform (PAL) Yellow Cyan Green Magenta Red Blue
Color Burst
PAL C Signal Output
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RGB Output Waveform
Semiconductor
B Signal
G Signal (Sync)
G Signal (no Sync)
R Signal
MR1[5] = 0
207
510
717
510
510
0
0
0
0
white
white
white
white
yellow
yellow
yellow
yellow
cyan
cyan
cyan
cyan
green
green
green
green
magenta
magenta
magenta
magenta
red
red
red
red
blue
blue
blue
blue
black
black
black
black
MSM7654
26/42
Semiconductor
B Signal
G Signal (Sync)
G Signal (no Sync)
R Signal
MR1[5] = 1
239
470
677
470
470
32
32
32
0
white
white
white
white
yellow
yellow
yellow
yellow
cyan
cyan
cyan
cyan
green
green
green
green
magenta
magenta
magenta
magenta
red
red
red
red
blue
blue
blue
blue
black
black
black
black
MSM7654
27/42
Semiconductor NTSC (Interlaced)
MSM7654
Field 1
Reference subcarrier phase
NEGATIVE HALF CYCLE Burst relative -180 to B-Y axis
POSITIVE HALF CYCLE Burst relative 180 to B-Y axis
259
260
261 A
262 263
1
2 B D
3
4
5 C
6
7
8
17
18
19
E Field 2 Reference subcarrier phase
259
260
261 A
262 263
1
2 B D
3
4
5 C
6
7
8
17
18
19
E Field 3 Reference subcarrier phase
259
260
261 A
262 263
1
2 B D
3
4
5 C
6
7
8
17
18
19
E Field 4 Reference subcarrier phase
259
260
261 A
262 263
1
2 B D
3
4
5 C
6
7
8
17
18
19
E
Output timing (Interlaced NTSC)
28/42
Semiconductor
MSM7654
Symbol A B C D E
Name First equalizing pulse period (3H) Vertical synchronization period (3H) Second equalizing pulse period (3H) Burst pause period Vertical blanking period (20H)
Period Odd field (Even field) 259.5 to 262.5H 1 to 3H 4 to 6H 1 to 6,259.5 to 262.5H 1 to 17,259.5 to 262.5H
Output timing (Interlaced NTSC)
29/42
Semiconductor
MSM7654
NTSC (Non-interlaced)
NEGATIVE HALF CYCLE Burst relative -180 to B-Y axis Reference subcarrier phase POSITIVE HALF CYCLE Burst relative 180 to B-Y axis
Continuous Odd Field
260
261 A
262
1
2 B D
3
4
5 C E
6
7
8
17
18
19
Reference subcarrier phase
260
261 A
262
1
2 B D
3
4
5 C E
6
7
8
17
18
19
Continuous Even Field
Reference subcarrier phase
260
261 A
262
1
2 B D
3
4
5 C E
6
7
8
17
18
19
Reference subcarrier phase
260
261 A
262
1
2 B D
3
4
5 C E
6
7
8
17
18
19
Output timing (Non-interlaced NTSC)
Period Continuous odd * even field 261 to 262H 1 to 3H 4 to 6H 261 to 6H 261 to 17H
Symbol A B C D E
Name First equalizing pulse period (2H) Vertical synchronization period (3H) Second equalizing pulse period (2H) Burst pause period Vertical blanking period (19H)
Output timing (Non-interlaced NTSC) 30/42
Semiconductor PAL (Interlaced)
Burst phase +135 +V Burst phase -135 -V
MSM7654
Field 1,5
309
310
311
312 313 A
1 B
2
3
4 C
5
6
7
8
23
24
25
D E Field 2,6
309
310
311
312 313 A
1 B D
2
3
4 C E
5
6
7
8
23
24
25
Field 3,7
309
310
311
312 313 A
1 B D
2
3
4 C E
5
6
7
8
23
24
25
Field 4,8
309
310
311
312 313 A
1 B
2
3
4 C
5
6
7
8
23
24
25
D E
Output timing (Interlaced PAL)
Symbol A B C D E Name Field 1,5 First equalizing pulse period (2.5H) Vertical synchronization period (2.5H) Second equalizing pulse period (2.5H) Burst pause period Vertical blanking period (25H) 311 to 312.5H 1 to 2.5H 2.5 to 5H 1 to 6,310 to 312.5H 1 to 22.5,311 to 312.5H Field 2,6 311 to 312.5H 1 to 2.5H 2.5 to 5H 1 to 5.5,308.5 to 312.5H 1 to 22.5,311 to 312.5H Period Field 3,7 311 to 312.5H 1 to 2.5H 2.5 to 5H 1 to 5,311 to 312.5H 1 to 22.5,311 to 312.5H Field 4,8 311 to 312.5H 1 to 2.5H 2.5 to 5H 1 to 6.5,309.5 to 312.5H 1 to 22.5,311 to 312.5H
Output timing (Interlaced PAL) 31/42
Semiconductor PAL (Non-interlaced)
Burst phase +135 +V Burst phase -135 -V
MSM7654
Continuous Odd Field
309
310
311 A
312
1 B
2
3
4 C
5
6
7
8
23
24
25
D E
309
310
311 A
312
1 B
2
3
4 C
5
6
7
8
23
24
25
D E Continuous Even Field
309
310
311 A
312
1 B
2
3
4 C
5
6
7
8
23
24
25
D E
309
310
311 A
312
1 B
2
3
4 C
5
6
7
8
23
24
25
D E
Output timing (Non-interlaced PAL)
Period Continuous odd * even field 311 to 312H 1 to 2.5H 2.5 to 5H 311 to 6H 311 to 22H
Symbol A B C D E
Name First equalizing pulse period (2H) Vertical synchronization period (2.5H) Second equalizing pulse period (2.5H) Burst pause period Vertical blanking period (24H)
Output timing (Non-interlaced PAL) 32/42
Semiconductor
q w e r q 1/2H w 1/2H e
MSM7654
Setting content of equalizing pulse vertical synchronization period (Ts is sampling clock cycle in each mode) q ITU 601 NTSC ITU 601 PAL 4Fsc NTSC w e 1/2H 31Ts 365Ts 64Ts 429Ts 32Ts 369Ts 63Ts 432Ts 33Ts 387Ts 68Ts 455Ts 28Ts 332Ts 58Ts 390Ts 35Ts 403Ts 69Ts 472Ts
qEqualizing pulse width qBlanking level Square pixel NTSC wVertical sync pulse width w(synchronizing + blanking level) (2/3) e(synchronizing + blanking level) (1/3) Square pixel PAL eSerration rSynchronzing level

1H
r e w q
t
q e r
w
t qHorizontal sync pulse width wBurst signal output period eBurst signal start rHorizontal blanking period (excluding front porch) tFront porch start qSynchronzing level w(synchronizing + blanking level) (1/3) e(synchronizing + blanking level) (2/3) rBlanking level tPeak to peak value of burst
Horizontal blanking period
Setting content of horizontal blanking period (Ts is sampling clock cycle in each mode) q ITU601 NTSC ITU601 PAL 4Fsc NTSC Square pixel NTSC Square pixel PAL 63Ts 63Ts 67Ts 58Ts 69Ts w 31Ts 31Ts 36Ts 31Ts 34Ts e r t Total dots/1H 858 864 910 780 944 71Ts 127Ts 838Ts 75Ts 142Ts 844Ts 65Ts 135Ts 889Ts 65Ts 116Ts 762Ts 82Ts 155Ts 922Ts
Setting content of horizontal blanking period 33/42
Semiconductor Setup Level Setting
MSM7654
When the NTSC operation mode is selected, one of the two kinds of setup level can be selected by setting of registers. When the setup level 0 is selected, the Black-to-White is 100IRE. When the setup level 7.5IRE is selected, the Black-to-White is 92.5IRE. However, this setup function is valid only for the NTSC mode and invalid for the PAL mode. Color Bar Generation Function The 75% luminance order color bar or 100% luminance order color bar is output by setting internal registers. The output timings for each color bar color is as follows.
White
Yellow
Cyan Green Magenta
Red
Blue
Black
q w e r t y u
Output timing of each color bar color
Operation mode ITU601 NTSC ITU601 PAL 4Fsc NTSC Square pixel NTSC Square pixel PAL (Ts : sampling clock period)
hblank 127Ts 142Ts 135Ts 116Ts 155Ts
q 216Ts 230Ts 230Ts 197Ts 251Ts
w 305Ts 318Ts 325Ts 278Ts 347Ts
e 394Ts 406Ts 419Ts 395Ts 443Ts
r 483Ts 494Ts 513Ts 440Ts 539Ts
t 572Ts 582Ts 607Ts 521Ts 635Ts
y 661Ts 670Ts 701Ts 602Ts 731Ts
u 750Ts 757Ts 795Ts 682Ts 827Ts
1H 858Ts 864Ts 910Ts 780Ts 944Ts
Contents of color bar output timing setting 34/42
Semiconductor
MSM7654
I2C BUS FORMAT
Basic input format of I2C-bus interface is shown below.
S
Slave Address
A
Subaddress
A
Data 0
A
.....
Data n
A
P
Symbol S Slave Address A Subaddress Data n P Start condition
Description Slave address 1000100X (ADRS pin : 0) the 8th bit is R (1)/W (0) signal. Acknowledge. Generated by slave Subaddress byte Write to the address specified by the subaddress. Stop condition
As described above, it is possible to write data from subaddress to subaddress continuously. Writing to discontinuous addresses is performed by repeating the Acknowledge and Stop condition formats after Data 0. If one of the following matters occurs, the encoder will not return "A" (Acknowledge). * The slave address does not match. * A non-existent subaddress is specified. * The write attribute of a register does not match "X" (write : 0 control bit). The input timing is shown below.
SDA SCL
1
2
8
ACK
1
2
8
ACK
1
2
8
ACK
S Start Condition
Slave Address
Slave Address
Data
P Stop Condition
I2C-bus Basic Input/Output Timing
35/42
Semiconductor
MSM7654
INTERNAL REGISTERS
All registers can be written. Details of the internal registers are described below.
Register name MR0 (Mode register) R/W Write Only Sub-address 00 MR0 [7] Item to be set Override Description Switching between the externalterminal and internal register settings(for the operation mode) *0 : External terminal setting enabled 1 : Internal register setting enabled MR0 [6] Chroma format Chrominance signal input format *0 : Offset binary 1 : 2's complement MR0 [5] DAC sleep control MR0 [4] RGBMODE DAC sleep mode Control *0 : DAC active 1 : DAC sleep Input signal switching *0 : YCbCr 1 : RGB Valid only in MODE [3:0] set as follows : (0101/0110/0111/1101/1110) MR0 [3:0] Video mode select Operation mode switching Corresponds to the external MODE [3:0] pin. The sleep mode is valid only when RGBMODE is "0". The sleep mode by the register isvalid for DAC only. *0000 : NTSC ITU-R656 0001 : NTSC 27 MHz YCbCr 0010 : NTSC 24.52 MHz Square Pixel 0011 : NTSC 28.64 MHz 4Fsc 0101 : NTSC 13.5 MHz YCbCr 0110 : NTSC 12.27 MHz 0111 : NTSC 14.32 MHz 1000 : PAL ITU-R656 1001 : PAL 27 MHz YcbCr 1010 : PAL 29.5 MHz Square Pixel 1101 : PAL 13.5 MHz 1110 : PAL 14.75 MHz 1111 : Sleep Mode
36/42
Semiconductor
MSM7654
Register name MR1 (Mode register)
R/W Write Only
Sub-address 01 MR1 [7]
Item to be set Black level Control
Description Black level setup Note : Valid in NTSC mode only *0 : Black level 0IRE 1 : Black level 7.5IRE
MR1 [6]
Counter Control
Non-standard signal input mode switching 0 : Corresonds to standard signal only 1 : Corresponds to standard and non-standard signals.
MR1 [5]
RGB input Level
RGB input level switching RGB input level *0 : 0 to 255 1 : 16 to 235 RGB output level *0 : 0 to 510 1 : 32 to 470
MR1 [4]
OUTSEL
Output signal switching *0 : S-video/composite 1 : RGB
MR1 [3]
Master/Slave
Master/Slave operation switching *0 : Slave 1 : Master
MR1 [2]
INTERLANCE
Scanning *0 : Interlace 1 : Non-interlace
MR1 [1]
Genlock Control
Genlock function On/Off control *0 : Genlock On 1 : Genlock Off Switching vetween Genlock control by the external pin and control by the internal register. *0 : External pin Genlock control is valid 1 : Internal register control is valid
MR1 [0]
Genlock Select
37/42
Semiconductor
MSM7654
Register name Register)
R/W
Sub-address 02 CR0 [6]
Item to be set CSYNC output
Description Addition control of CSYNC_Lat RGB *0 : Addition of CSYNC 1 : No addition of CSYNC to G signal
CR0 (Command Write Only
CR0 [5]
FOUT
FOUT palarity change *0 : Odd field "L", Even field "H" 1 : Odd field "H", Even field "L"
CR0 [4]
Trap Filter
TRAP filter On/Off control *0 : Trap filter Off 1 : Trap filter On
CR0 [3]
Color Bar
Adjusting luminance ordercolor bar output control *0 : Input image data or overlay data 1 : Luminance order color bar
CR0 [2:1]
Overlay level
Overlay signal/adjusting luminance order color bar output level control 11 : 25% 10 : 50% 01 : 75% *00 : 100%
CR0 [0]
Sampling rate
Sampling rate control *0 : 4:2:2 1 : 4:1:1
CR1 (Command Write Only Register)
03
CR1 [3:0]
Luminance Level
Adjusting luminance levelof input image data *0000 : 100.00% 0001 : 96.875% 0010 : 93.750% 0011 : 90.675% 0100 : 87.500% 0101 : 84.375% 0110 : 81.250% 0111 : 78.125% 1000 : 75.000% 1001 : 71.875% 1010 : 68.750%
38/42
Semiconductor
MSM7654
FILTER CHARACTERISTICS
The characteristics of LPF used for color signal processing and interpolation filters used for upsampling processing are shown below. LPF for 422 color signals The following shows the characteristics when the clock frequency is 13.5 MHz.
0
-20
Level [dB]
-40
-60
-80
-100 0 1 2 3 4 Frequency [MHz] 5 6 7
422 Interpolation + LPF Frequency Characteristic
Interpolation The following shows the characteristics when the clock frequency is 27 MHz.
0
-20
Level [dB]
-40
-60
-80
-100 0 2 4 6 8 Frequency [MHz] 10 12 14
Up Sampling Filter Frequency Characteristic
(Note) The characteristics of these filters are based on design data. 39/42
Semiconductor Trap Filter The following shows the characteristics when the clock frequency is 27 MHz.
Trap Filter (for NTSC) Frequency Characteristics 0
MSM7654
-20
Level [dB]
-40
-60
-80
-100 0 1 2 3 4 Frequency [MHz] 5 6 7
Trap Filter (for PAL) Frequency Characteristics 0
-20
Level [dB]
-40
-60
-80
-100 0 1 2 3 4 Frequency [MHz] 5 6 7
(Note) The characteristics of these filters are based on design data.
40/42
Semiconductor
MSM7654
APPLICATION CIRCUIT EXAMPLE (YCbCr 16-bit input mode)
5 V or 3.3 V
RL 5 V or 3.3 V I2C Controller
RL 3.3 V 3.3 V
MS RGBMODE MODE[3:0] TENB OUTSEL OLR OLG OLB OLC
DVDD
DIP SW
AVDD
SDA
SCL
XVREF
Typ. 1.25 V 3.3 V RC CC = 0.1 F
FS
COMP LPF YA MSM7654 CVBSO R1 R1 LPF CA R1 DGND AGND CLKX2 FOUT RC = 500 VR R1 R1 LPF R1
Overlay Controller 5 V or 3.3 V YD[7:0] CD[7:0] BD[7:0] (0 fixed)
YD[7:0] CD[7:0] BD[7:0] VSYNC_L HSYNC_L BLANK_L CSYNC_L
Sample of Analog Output Circuit
YA CA CVBSO OUTPUT 150 W
3.6 mH 150 W 164 pF 164 pF
LPF (TOKO, INC 628LJN-1471 is recommended.)
Note: The termination of a DA converter analog output with a 37.5 W load eliminates need for an AMP.
41/42
Semiconductor
MSM7654
PACKAGE DIMENSIONS
(Unit : mm)
Mirror finish
64-Pin Plastic QFP
42/42
E2Y0002-28-41
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents cotained herein may be reprinted or reproduced without our prior permission.
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Copyright 1998 Oki Electric Industry Co., Ltd.
Printed in Japan

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